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rev. 1.0 7/13 copyright ? 2013 by silicon laboratories SI4684-A10 SI4684-A10 s ingle - chip , f m /d ab /d ab + r adio r eceiver features applications description the si4684 single-chip digital receiver is one member of a family of 100% cmos digital radio broadcast receiver ics from silicon labs. the si46xx family provides revolutionary advanc es in size, power consumption, and performance to enable high-volume, cost-sensitive multimedia products to incorporate digital broadcast features. the family offers all-in-one, ultra-low power, multi-band digital broadcast receivers to support global analog and digital radio standards including am, sw, lw, fm, fm rds, hd, dab, dab+, dmb, and drm(30). ? worldwide fm band support (76?108 mhz) ? advanced rds/rbds decoder ? dab, dab+ band iii support (168?240 mhz) ? supports worlddmb receiver profiles 1 and 2 ? ofdm channel demodulator ?? simultaneous decoding of up to 4 service components ?? seamless dynamic multiplex reconfiguration ? integrated sram supporting time and frequency de-interleaving ? advanced seek functionality ? advanced audio dsp processing ? complete on-chip source decode ? i 2 s digital audio out with asrc ? integrated 97 db stereo audio dac ? concurrent i 2 s / l-r stereo audio out ? full range of analog and digital signal quality metrics ? fully-integrated vco / pll / synthesizer ? fully-integrated advanced agc and alignment ? spi, i 2 c control interfaces ? fm sensitivity = 0.7 v ? dab sensitivity = ?101 dbm ? wlcsp and qfn packages ? mobile phones and tablets ? clock and tabletop radios ? personal navigation devices ? stereo boomboxes ? mini/micro systems ? docking stations patents pending ordering information: see page 35.
SI4684-A10 2 rev. 1.0 functional block diagram i2s flash interface lout rout rfref nvsclk nvssb nvmosi nvmiso vhfi xtali xtalo adc dac dclk dfs dout sclk ssb miso mosi clk gen rds control intb rstb ldos SI4684-A10 agc adc dac dsp lna vio va vcore vmem vhfsw vhf sw
SI4684-A10 rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.2. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3. tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4. fm receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5. dab radio receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.6. stereo audio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7. fm seek and valid station qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.8. rds/rbds decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5. audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1. analog audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2. digital audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6. control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1. spi control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 6.2. i2c control bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 6.3. programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 6.4. serial flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.5. reset timing and power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1. SI4684-A10-gm pin descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2. SI4684-A10-gd pin descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9. package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 9.1. SI4684-A10-gm package outl ine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2. SI4684-A10-gd package outl ine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10. pcb land patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 10.1. SI4684-A10-gm pcb land pa ttern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2. SI4684-A10-gd pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11. top markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.1. SI4684-A10-gm top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.2. SI4684-A10-gm top mark explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.3. SI4684-A10-gd top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.4. SI4684-A10-gd top marki ng explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
SI4684-A10 4 rev. 1.0 1. electrical specifications table 1. recommended operating conditions* parameter symbol test condition min typ max unit analog supply voltage v a 1.71 1.8 2.0 v interface supply voltage v io 1.62 1.8 3.6 v core digital supply voltage v core 1.62 1.8 2.0 v memory supply voltage v mem 1.62 1.8 2.0 v *note: all minimum (min) and maximum (max) specifications are guaranteed and apply across the recommended operating conditions. typical (typ) values apply at va = vio = vcore = vmem = 1.8 v, and 25 c unless otherwise stated. parameters are tested in pr oduction unless otherwise stated.
SI4684-A10 rev. 1.0 5 table 2. dc characteristics 1,2 (t amb = 25 c, va = vio = vmem = vcore = 1.8 v) parameter symbol test condition min typ max unit reset va rstb pin = low ? 0.5 5 a vcore ? 1 8 a vmem ? 1 8 a vio ?0.53 a startup va rstb pin = high ? 1 ? a vcore ? 8.5 ? ma vmem ? 1 ? ma vio ?160? a operational?analog fm mode va analog fm reception ? 19.1 22.7 ma vcore ? 7.4 9.1 ma vmem ? 4.8 6.2 ma vio ?0.10.1ma operational?dab/dab+ mode 3 va dab/dab+ rece ption ? 23.9 25.0 ma vcore ? 14.0 17.0 ma vmem ? 9.0 13.3 ma vio ?0.30.6ma notes: 1. power states are described in section ?6.5. reset timing and power states? . 2. characteristics apply to firmware fm 2.0.10 and firmware d ab 1.0.6. for later firmware versions see ?si468x data sheet addendum?. parameters are tested in production unless otherwise stated. 3. guaranteed by characterization. 4. for input pins rstb, smode, sclk , ssb, mosi, nvmiso, dclk and dfs. 5. for output pins intb , miso, nvsbb, nvsclk, nvmosi and dout.
SI4684-A10 6 rev. 1.0 i/o voltages and currents high level input voltage 4 v ih 0.7 x v io ?? v low level input voltage 4 v il ?? v high level input current 4 i ih v io = 3.6 v ? a low level input current 4 i il v io = 3.6 v ? a high level output voltage 5 v oh i out = 500 a ? ? v low level output voltage 5 v ol i out = ?500 a ? ? v table 2. dc characteristics 1,2 (continued) (t amb = 25 c, va = vio = vmem = vcore = 1.8 v) parameter symbol test condition min typ max unit notes: 1. power states are described in section ?6.5. reset timing and power states? . 2. characteristics apply to firmware fm 2.0.10 and firmware d ab 1.0.6. for later firmware versions see ?si468x data sheet addendum?. parameters are tested in production unless otherwise stated. 3. guaranteed by characterization. 4. for input pins rstb, smode, sclk , ssb, mosi, nvmiso, dclk and dfs. 5. for output pins intb , miso, nvsbb, nvsclk, nvmosi and dout.
SI4684-A10 rev. 1.0 7 figure 1. spi control interface timing parameters table 3. spi control interface characteristics 1,2,3 (t amb = ?40 to 85 c, va = 1.71 to 2.0 v, vio = 1.62 to 3.6 v, vmem = vcore = 1.62 to 2.0 v) parameter symbol test condition min typ max unit sclk frequency f sclk ??10mhz sclk high time 3 t hi 20 ? ? ns sclk low time 3 t lo 20 ? ? ns input rise time 3 t f ??20 ns input fall time 3 t r ??20 ns ssb setup to sclk rise 3 t su:ssb 10 ? ? ns ssb hold from sclk fall 3 t h:ssb 0?? ns mosi setup to sclk rise 3 t su:mosi 10 ? ? ns mosi hold from sclk fall 3 t h:mosi 0?? ns miso output delay from sclk fall 3 t pd 0?20 ns miso drive delay from ssb fall 3 t d ??20 ns miso tristate delay from ssb rise 3 t z ??20 ns capacitive loading 3 c b ? ? 50 pf notes: 1. the spi interface transparently supports mode 0,0 and mode 1,1, both of which use the rising edge of the clock to capture data. the user must not pu lse ssb high between each byte, becaus e ssb is used to frame commands and replies. ssb must be held low for the duration of the spi trans action, and raised at the end to signal the completion of a command write or a reply read. 2. see spi control interface protocol in figure 9, ?si4684 spi control interfac e bus protocol ? spi mode 0,0? and figure 10, ?si4684 spi control interfac e bus protocol ? spi mode 1,1?. 3. guaranteed by characterization. sclk ssb mosi miso msb msb-1 msb-2 lsb+2 lsb+1 lsb msb msb-1 msb-2 lsb+2 lsb+1 lsb t su:mosi t h:mosi t pd max t pd min t hi t lo t f t su:ssb t d t r t h:ssb t z t f t r t f t r
SI4684-A10 8 rev. 1.0 figure 2. i 2 c control interface timing parameters table 4. i 2 c control interface characteristics* (t amb = ?40 to 85 c, va = 1.71 to 2.0 v, vio = 1. 62 to 3.6 v, vmem = vcore = 1.62 to 2.0 v) parameter symbol test condition min typ max unit scl frequency f scl 0 ? 400 khz scl high time t hi 0.6 ? ? s scl low time t lo 1.3 ? ? s scl input to sda ? setup (start) t su:sta 0.6 ? ? s scl input from sda ? hold (start) t hd:sta 0.6 ? ? s sda input to scl ? setup t su:dat 100 ? ? ns sda input from scl ? hold t hd:dat 0??ns sda output delay t pd:dat 50 ? 900 ns scl input to sda ? setup (stop) t su:sto 0.6 ? ? s stop to start time t buf 1.3 ? ? s sda output fall time t f:out ? 150 ns sda input, scl rise/fall time t f:in, t r:in 0 ? 300 ns capacitive loading c b ? ? 50 pf pulse width rejected by input filter t sp ? ? 50 ns *note: guaranteed by characterization. 20 0.1 c b 1pf ---------- - + scl sda t su:sta t hd:sta t lo start t r:in t hd:dat t su:dat t hi t r:in t f:in t pd:dat t sp t su:sto t f:in, t f:out, stop start t buf
SI4684-A10 rev. 1.0 9 figure 3. digital audio interface timing parameters table 5. i 2 s digital audio interface characteristics * (t amb = ?40 to 85 c, va = 1.71 to 2.0 v, vio = 1.62 to 3.6 v, vmem = vcore = 1.62 to 2.0 v) parameter symbol test condition min typ max unit dclk frequency f dclk ?? 15 mhz dclk input cycle time t cyc:dclk 66.7 ?? ns dclk input pulse width high t hi:dclk 20 ? ? ns dclk input pulse width low t lo:dclk 20 ? ? ns dfs setup time t su:dfs 5?? ns dfs hold time t hd:dfs 5?? ns dout output delay t pd:dout 0 ? 10 ns capacitive loading c b ? ? 50 pf *note: guaranteed by characterization. t hd:dfs t su:dfs t cyc:dclk t pd:dout t hi:dclk t lo:dclk dclk in dfs in dout out
SI4684-A10 10 rev. 1.0 figure 4. serial flash interface timing parameters table 6. serial flash interface characteristics 1,2 (t amb = ?40 to 85 c, va = 1.71 to 2.0 v, vio = 1. 62 to 3.6 v, vmem = vcore = 1.62 to 2.0 v) parameter symbol test condition min typ max unit nvsclk frequency f nvsclk ??40mhz nvsclk high time t hi 10 ? ? ns nvsclk low time t lo 10 ? ? ns input/output rise time t r ??20 ns input/output fall time t f ??20 ns nvssb setup to nvsclk rise t su:nvssb 10 ? ? ns nvssb hold from nvsclk fall t h:nvssb 0?? ns nvmosi setup to nvsclk rise t su:nvmosi 10 ? ? ns nvmosi hold from nvsclk fall t h:nvmosi 0?? ns nvmiso setup to nvsclk rise t su:nvmiso 10 ? ? ns nvmiso hold from nvsclk rise t h:nvmiso 10 ? ? ns notes: 1. the serial flash interface supports spi mode 1,1, which uses the rising edge of the clock to capture data. 2. guaranteed by characterization. nvsclk (out) nvssb (out) nvmosi (out) nvmiso (in) msb msb-1 msb-2 lsb+2 lsb+1 lsb msb msb-1 msb-2 lsb+2 lsb+1 lsb t su:nvmosi t su:nvmiso t hi t lo t f t su:nvssb t r t h:nvssb t h:nvmosi t r t r t h:nvmiso t f t f
SI4684-A10 rev. 1.0 11 table 7. analog fm receiver characteristics 1,2,3 (t amb = ?40 to 85 c, va = 1.71 to 2.0 v, vio = 1.62 to 3.6 v, vmem = vcore = 1.62 to 2.0 v) parameter symbol test condition min typ max unit input frequency f rf 76 ? 108 mhz audio sensitivity 4 sinad = 26 db ? 0.7 1.0 v rds sensitivity 4,5 f dev = 2 khz, rds bler < 5%, analog audio output mode ?4 ? v input ip3 5 |f 2 ? f 1 | > 2 mhz, f 0 = 2 x f 1 ? f 2 , agc is disabled 90 96 ? db v image rejection 5 35 45 ? db am suppression 5 f dev = 22.5 khz 53 58 ? db adjacent channel selectivity 200 khz 35 50 ? db alternate channel sele ctivity 400 khz 35 43 ? db audio output voltage f dev = 22.5 khz 48 52 55 mvrms audio output l/r imbalance f dev = 75 khz ?1 ? 1 db audio frequency response low 5 3 db ? ? 30 hz audio frequency response high 5 3 db 15 ? ? khz audio stereo separation f dev = 75 khz 35 45 ? db audio mono snr f dev = 22.5 khz 62 68 ? db audio stereo snr 5 f dev = 22.5 khz ? 60 ? db audio mono thd f dev = 75 khz ? 0.1 0.5 % audio mono sinad f dev = 75 khz 60 ? ? db de-emphasis time constant 5 fm_deemphasis = 75 s7075 80 s fm_deemphasis = 50 s4550 54 s seek/tune time 5 tune mode = 0 (fm analog mode) ?? 60ms/ch rssi offset rf input levels of 0 and 60 db v ?3 ? 3 db notes: 1. characteristics apply to firmware fm 2.0.10. for late r firmware versions see ?si468x data sheet addendum?. parameters are tested in production unless otherwise stated. 2. test setup and test conditions are available in ?an651: si46 xx evaluation board test procedure?. tested at rf = 98.0 mhz. 3. to ensure proper operation and receiver performance, follo w the guidelines in ?an650: si46xx schematic and layout guide?. silicon laboratories will evaluate schematics and layouts for qualified customers. 4. signal generator reading. voltage at vhf pin typically 6 db higher. 5. guaranteed by characterization.
SI4684-A10 12 rev. 1.0 table 8. dab receiver characteristics 1,2,3 (t amb = ?40 to 85 c, va = 1.71 to 2.0 v, vio = 1. 62 to 3.6 v, vmem = vcore = 1.62 to 2.0 v) parameter symbol test condition min typ max unit input frequency 4 f rf 168 ? 240 mhz input ip3 4 lna gain = 5 db ? 103 ? db v sensitivity 4 ber = 10 -4 lna gain = 15 db ?2.0 ? v ? ?101 ? dbm first adjacent selectivity 4,5 ber = 10 -4 , 1.712 mhz ? 46 ? db second adjacent selectivity 4,5 ber = 10 -4 , 3.424 mhz ? 48 ? db third adjacent selectivity 4,5 ber = 10 -4 , 5.136 mhz ? 48 ? db ensemble acquisition time 4,6 for a valid channel, after powerup rf level = ?47 dbm ?940 ? ms notes: 1. characteristics apply to firmware dab 1.0.6. for later firmware versions see ?si468x data sheet addendum?. parameters are tested in production unless otherwise stated. 2. test setup and test conditions are available in ?an651: si46xx evaluation board test procedure?. tested at rf = 195.936 mhz. 3. to ensure proper operation and receiver performance, follow the guidelines in ?an650: si46xx schematic and layout guide?. silicon laboratories will evaluate schematics and layouts for qualified customers. 4. guaranteed by characterization. 5. in selectivity measurements, rf blocker used is concord with the mask defined in section 7.3.3.1.1 in en50248 (2001). 6. time measured from the completion of the dab tuning command to the setting of the acq bit indicating ensemble acquisition. for eti filed used in ber test see an651.
SI4684-A10 rev. 1.0 13 table 9. reference clock and crystal characteristics 1 (t amb = ?40 to 85 c, va = 1.71 to 2.0 v, vio = 1. 62 to 3.6 v, vmem = vcore = 1.62 to 2.0 v) parameter symbol test condition min typ max unit reference clock reference clock frequency rclk n x 5.4 (see note 2 ) n x 6.0 (see note 2 ) n x 6.6 (see note 2 ) mhz reference clock accuracy ?50 ? 50 ppm reference clock duty cycle 45 ? 55 % reference clock phase noise see mask in figure 5 ? ? ? ? crystal oscillator crystal frequency n x 5.4 (see note 2 ) n x 6.0 (see note 2 ) n x 6.6 (see note 2 ) mhz crystal accuracy ?50 ? 50 ppm crystal load capacitance 3,4 6mhz (500 ? startup esr) 5 ? 30 pf 36.864 mhz (400 ? startup esr) 5?7.5pf crystal startup esr 3 6mhz (30 pf load capacitance) ??500 ? 36.864 mhz (7.5 pf load capacitance) ??400 ? notes: 1. guaranteed by design. 2. n = 1,2,3,4,5,6. 3. refer to ?an649: si46xx programming guide?, section 8 for further details on how to choose crystal for si46xx application. 4. if load capacitance > 14 pf, it requires two external ca pacitances due to limits in the internal tuning range.
SI4684-A10 14 rev. 1.0 figure 5. reference clock phase noise mask (referred to 6 mhz)
SI4684-A10 rev. 1.0 15 table 10. thermal conditions parameter symbol test co ndition min typ max units ambient temperature t a ? ?40 25 85 c junction temperature * t j ? ja (qfn) ~ 25 c/w ? ? 90 c ? ja (wlcsp) ~ 33.5 c/w ? ? 90 c *note: the ? ja performance is layout and package dependent . application recommendations to follow. table 11. absolute maximum limits parameter symbol test condition min max units analog supply voltage 1,2 v a ?0.3 2.2 v interface supply voltage 1,2 v io ?0.3 3.9 v core digital supply voltage 1,2 v core ?0.3 2.2 v memory supply voltage 1,2 v mem ?0.3 2.2 v input voltage 1,2,3 v in ?0.3 v io +0.3 v input current 1,2,3 i in ?10ma operating temperature 1,2 t op ?45 95 c storage temperature 1,2 t stg ?55 150 c rf input level 1,2,4 rf in ?0.3 1.7 v pk rf input level 1,2,5 rf in ?13dbm hbm esd v hbm qfn ? 4000 v wlcsp ? 4000 v cdm esd v cdm qfn ? 1000 v wlcsp ? 900 v mm esd v mm qfn ? 300 v wlcsp ? 300 v notes: 1. permanent device damage may occur if the absolute ma ximum ratings are exceeded. functional operation should be restricted to the conditions as specif ied in the operational sections of this data sheet. exposure beyond recommended operating conditions for extended per iods may affect device reliability. 2. guaranteed by design. 3. for input pins rstb, smode, sclk , ssb, mosi, nvmiso, dclk and dfs. 4. at analog pins xtali, xtalo. 5. at rf pin vhfi and vhfsw.
SI4684-A10 16 rev. 1.0 2. typical application schematic *note: the application schematic assumes that the headphone amplifier uses true ground as hpout_com. u1 va lout rout nvsclk nvssb nvmosi nvmiso sclk ssb mosi miso dclk dfs dout rstb smode intb gnda vmem vio vcore sclk ssb mosi miso rstb intb lout rout dclk dfs dout optional ? digital ? audio flash optional ? serial ? flash u2 r1 ??? ??? ??? antenna ? feed dacref gnda c3 2.2nf c2 5.6pf va ? (1.71 \ 2.0v) vio ? (1.62 \ 3.6v) vmem (1.62 \ 2.0v) vcore (1.62 \ 2.0v) fb1 hpout_l fb2 hpout_r fb3 hpout_com hp_jack d1 d2 d3 c12 100pf c13 100pf c14 100pf c5 1uf c6 2.2nf c7 2.2nf c8 2.2nf dbyp xtali xtalo x1 clkin optional ? crystal vhfi vhfsw rfref smode c1 100pf l1 120nh l2 36nh
SI4684-A10 rev. 1.0 17 3. bill of materials table 12. bill of materials required component(s) value/description u1 si4684 digital radio receiver l1 tuning inductor, 120 nh, 0603 wire wound l2 tuning inductor, 36 nh, 0603 wire wound c1 band tuning cap, 100 pf c2 va supply bypass capacitor, 5.6 pf c3, c6, c7, c8 supply bypass capacitor, 2.2 nf, z5u/x7r c4 supply bypass capacitor, 0.1 f, z5u/x7r c5 supply bypass capacitor, 1 f c12, c13, c14 filter capacitor, 100 pf fb1, fb2, fb3 ferrite bead filter, 1 k ? d1, d2, d3 esd protection diode optional component(s) value/description x1 crystal u2 serial flash, 16 mb, microchip sst25 r1, r2 resistor, 2 k ? r3 resistor, 600 k ?
SI4684-A10 18 rev. 1.0 4. functional description 4.1. overview figure 6. si4684 block diagram the si4684 offers a complete and cost-effective platform to support global analog vhf band ii and digital vhf band iii radio standards by integrating multiband rf tuner, demodulator, channel decoder, and audio processing on a single die. the high level of integration and complete system production test simplifies design-in, increases system quality, and improves reliability an d manufacturability. the si4684 supports worldwide analog fm radio reception and incorporates a fully integrated decoder for the european radio data system (rds) and the north american radio broadcast data system (rdbs), including all required symbol decoding, block synchronization, error detection, and error correction functions. the si4684 additionally supports digital dab and dab+ reception, incorporating digital channel demodulation and decoding functions, along with audio decoding. leveraging silicon laborator ies' proven and patented digital low intermediate fr equency (low-if) receiver architecture, the si4684 delivers superior rf performance and interference rejection. the solution offers auto-calibrated digital tuning, and proven fm seek functionality based on multiple signal quality and band parameters. the si4684 offers highly flexible and advanced audio processing including noise blanking, programmable soft mute, fm stereo-mono blend, and fm hi-cut filters. in addit ion, the si4684 provides an integrated clock o scillator or accepts a reference clock and supports a selectable control interface (spi or i 2 c). the si4684 receiver system requires a minimal bill of materials and offers extremely low power consumption, making the solution ideal for handheld and portable consumer electronic devices. 4.2. clocking the si4684 generates all internal clocking from an external crystal using an on-chip oscillator or an external programmable reference clock. the reference clock of si4684 is a sinuso idal or rectangular clock provided by an external source on pin xtali. the power_up command enables the selection of an external crystal or referenc e clock. the si4684 features programmable loading capacitors for the on-chip crystal oscillator, eliminating exte rnal loading capacitors. 4.3. tuning the si4684 includes a complete, fully integrated pll- vco frequency synthesizer to generate the quadrature local oscillator (lo) input to the vhf mixer. no external loop filter capacitors or vco inductors are required. the fm and dab tuning commands automatically configure the frequency synthesizer to generate the appropriate lo frequency to receive the desired channel. i2s flash interface lout rout rfref nvsclk nvssb nvmosi nvmiso vhfi xtali xtalo adc dac dclk dfs dout sclk ssb miso mosi clk gen rds control intb rstb ldos SI4684-A10 agc adc dac dsp lna vio va vcore vmem vhfsw vhf sw
SI4684-A10 rev. 1.0 19 4.4. fm receiver the si4684 fm receiver is based on silicon laboratories? proven fm radio family. the part leverages silicon laborator ies' proven and patented low-if digital architecture, delivering excellent rf performance and interference rejection. the proven digital techniques provide ex cellent sensitivity in weak signal environments while providing superb selectivity and inter-modulation immunity in strong signal environments. the si4684 supports the worldwide fm broadcast band (76?108 mhz) with channel spacings of 50, 100, and 200 khz. the low-if archit ecture utilizes a single converter stage and digitizes the audio signal using a high-resolution analog-to-digital converter. the stereo audio output can be direct ed either to an external headphone amplifier via the lout and rout pins or to other system ics through a digital audio interface (i 2 s). 4.4.1. fm received signal qualifiers a tuned signal's quality can va ry with the environmental conditions, time of day, and geographical location among many other factors. to adequately manage the audio output and avoid unpleasant audible effects to the end-user, the si4684 monitors and provides indicators of signal quality, allowing the on-chip dsp and host processor (if required) to perform signal processing. the si4684 monitors and reports a set of industry- standard signal quality metrics including on-channel rssi, snr, multipath interference on fm signal and fm pilot detection. 4.4.2. fm de-emphasis pre-emphasis and de-emphasis is a technique used by fm broadcasters to improve the signal-to-noise ratio of fm receivers by reducing the effects of high-frequency interference and noise. when the fm signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. the si4684 incorporates a de-emphasis f ilter which attenuates high frequencies to restore a flat frequency response. two time constants are used in various regions. the de- emphasis time constant is programmable to 50 or 75 s. 4.4.3. fm soft mute the soft mute feature is available to attenuate the audio outputs and minimize audible noise in compromised signal conditions. the si4684 triggers soft mute by monitoring signal metrics such as audio snr. the thresholds for activating soft mute are programmable, as are soft mute attenuation levels and attack and decay rates. the si4684 provides the soft mute feature in the fm band. 4.4.4. fm hi-cut control hi-cut control is employed on the si4684 audio outputs with degradation of signal quality. signal quality metrics such as audio snr, on-channel rssi, and multipath snr are monitored concurrently in forcing hi-cut of the audio outputs. programmable minimum and maximum thresholds are available for all metrics. attack and release rates for hi-cut are programmable for all metrics. hi-cut can be disabled by setting the hi-cut filter setting to the default audio bandwidth for fm. 4.5. dab radio receiver the si4684 dab radio receiver offers vhf band iii (168?240 mhz) reception capability and is fully compliant with etsi en 300 401 (dab) and etsi ts 102 563 (dab+). the si4684 dab receiver supports dab and dab+ via an integrated source decoder that supports both mpeg audio layer 2 (dab) and he-aac v2 (dab+). the stereo audi o output can be directed either to an external headphone amplifier via analog and/or to other system ics through an i 2 s digital audio interface. the si4684 dab receiver additionally supports data services such as dynamic labels, intellitext, electronic program guide (epg), slid eshow and journaline? with the appropriate external decoders.
SI4684-A10 20 rev. 1.0 4.6. stereo audio processing the output of the fm demodulator is a stereo multiplexed (mpx) signal. the mpx signal format consists of left + right (l+r) audio, left ? right (l?r) audio, a 19 khz pilot tone, and rds/rbds data as shown in figure 7, ?mpx signal spectrum?. figure 7. mpx signal spectrum 4.6.1. stereo decoder the si4684 integrated stereo decoder automatically decodes the mpx signal using dsp techniques. the 0?15 khz (l+r) signal is the mono output of the fm tuner. stereo is generated from the (l+r), (l?r), and a 19 khz pilot tone. the pilot tone is used as a reference to recover the (l?r) signal. output left and right channels are obtained by adding and subtracting the (l+r) and (l?r) signals respectively. 4.6.2. stereo-mono blending adaptive noise suppression is employed to gradually combine the stereo left and right audio channels to a mono (l+r) audio signal as the signal quality degrades to maintain optimum sound fidelity under varying reception conditions. signal quality metrics such as on- channel rssi and multipath snr are monitored simultaneously in forcing a blend from stereo to mono. the metric, reflecting the poorest signal quality, takes priority and the stereo signal is blended appropriately. the thresholds for activa ting stereo-mono blend are programmable, as are the levels for a fully blended state. the attack and decay rates for each metric are programmable. the pilot detection metric is additionally available for read-out. 4.7. fm seek and valid station qualification the fm seek function will search up or down the selected frequency band for a valid channel. a valid channel is qualified according to a series of programmable signal indicators and thresholds including rssi and snr. the seek function can be programmed to stop at the band edge or wrap at the band and continue seeking un til arriving at the original departure frequency. the device can be programmed to interrupt the host processor whenever the seek function is complete. seek is comple te when one of the following conditions are met: 1. a valid station is found. 2. no valid station is found and the stop frequency is found. the stop frequency can be programmed to either the band edge (no wrap) or the starting frequency (wrap). the si4684 seek functionality is performed completely on-chip. to facilitate this, the si4684 can provide real time updates for the signal quality metrics to host processor for station qualification. the si4684 uses rssi, snr, and frequency offset to qualify stations. these variables have programmable thresholds to tailor the seek function to the subj ective tastes of customers. rssi is employed first to screen all possible candidate stations. snr and frequency offset are subsequently used in screening the rssi qualified stations. the more thresholds the system engages, the higher the confidence that an y found stations will indeed be valid broadcast stations; however, the more challenging levels the thresholds are set to, the longer the overall seek time as more stations and more qualifiers will be assessed. it is recommended that rssi be set to a mid- level threshold in conjunction with an snr threshold set to a level delivering acceptable audio performance. this trade-off will eliminate very low rssi stations whilst keeping the seek time to acceptable levels. in addition to the programmable thresholds, both rssi and snr have programmable qualification times. these times can be made shorter to decrease the seek time or made longer to increase the robustness of the seek function. generally, the time to auto-scan and store valid channels for an entire fm band with all thresholds engaged is very short depending on the band content. seek is initiated using the fm_seek_start command. the rssi, snr and frequency offset thresholds and qualification time settings are adjustable using properties.
SI4684-A10 rev. 1.0 21 4.8. rds/rbds decoder the si4684 implements an adv anced, patented, high- performance rds/rbds* processor for demodulation, symbol decoding, block synchronization, error detection, and error correction. the rds decoder provides several significant benefits over traditional implementations, including very fast and robust rds synchronization in noisy si gnal levels with very high block error rates (bler), industry-leading sensitivity, and improved data reliability in all signal environments. the si4684 strong synchronization performance in very noisy/low snr environments minimizes the number of instances of lost synchronization. other less robust tuners must attempt to resynchronize in low snr environments, resulting in lost data and lengthy delays in re-establishing data reception. the si4684 maintains synchronization to the rds transmission, despite high bler. this results in fewer dropped connections, minimal resynchronization time, and greater data reliability in low snr environments. the si4684 reports rds decoder synchronization status and detailed bit errors in the information word for each rds block. the range of reportable block errors is 0, 1-2, 3-5, or 6+. more than six errors indicate that the corresponding block information word contains six or more non-correctable errors or that the block check word contains errors. the si4684 also provides highly configurable interrupts based on rds-driven events and conditions. the default settings provide an interrupt when rds is synchronized and when rds group data has been received. the configurable interrupts can be set to provide frequent interrupts down to a single received block with bler. the configurable interrupts also can be set to provide very infrequent interrupts, buffering up to 25 complete rds groups (100 blocks) with bler information by block in the on-chip fifo. the si4684 also provides configurable interrupts on changes or receipt of the key rds blocks a and b. this flexibility allows adopters to either conduct extensive rds data processing on the host or reserve the host processor in power-saving modes with minimal rds interrupts, allowing the si4684 to perform rds processing on-chip. *note: rds/rbds is referred to only as rds throughout the remainder of this document.
SI4684-A10 22 rev. 1.0 5. audio interface 5.1. analog audio high-fidelity digital-to-analog converters (dacs) drive analog audio signals onto the lout and rout pins. the audio output may be muted. volume is adjusted digitally. 5.2. digital audio interface the digital audio 3-pin interface consists of data serial li nes containing audio data, a bit clock, and a word frame for left and right channel data. the digital audio inte rface operates in slave mode and supports the i 2 s audio format. in the i 2 s audio format, by default the msb is captured on th e second rising edge of dclk following each dfs transition. the remaining bits of the word are sent in order, down to the lsb. the left channel is transferred first when the dfs is low, and the right channe l is transferred when the dfs is high. 5.2.1. audio sample rates the si4684 supports a number of industry-standard sampling rates including 32, 40, 44.1, and 48 khz. figure 8. i 2 s audio format
SI4684-A10 rev. 1.0 23 6. control interface two serial port slave protocols are supported, a serial peripheral (spi) control interface protocol and an i 2 c control bus interface protocol, which allow an external controller to send commands and receive responses from the si4684. 6.1. spi control interface the si4684 control interface operates in spi mode when the smode pin is tied to gnd. the si4684 spi control interface supports the synchronous transfer of data between the part and an external controller via a 4-wire bus consisting of: ?? a serial clock (sclk), provided by the external controller ?? a slave select (ssb), a llows the master to select a slave device ?? a slave data input pin (mosi) ?? a slave data output pin (miso) because all data transfers across the spi control interface are synchronized to the serial clock (sclk), there are four possible modes that can be used in an spi protocol, based on the serial clock?s phase (cpha) and polarity (cpol). the si4684 spi control interface supports spi mode 0 (cpha=0, cpol=0), and spi mode 3 (cpha=1, cpol=1). figure 9, ?si4684 spi control interface bus protocol ? spi mode 0,0? and figure 10, ?si4684 spi control interface bus protocol ? spi mode 1,1? show the spi control inte rface bus protocols for spi mo des 0 and 3, respectively. figure 9. si4684 spi control interface bus protocol ? spi mode 0,0 ssb msb msb-1 . . . lsb+1 lsb command (write) mosi msb msb-1 . . . lsb+1 lsb msb arg 1 msb-1 . . . lsb+1 lsb arg n miso zeros sclk ssb msb msb-1 . . . lsb+1 lsb 00 mosi . . . . . . . . . msb msb-1 . . . lsb+1 lsb msb status (response 0) msb-1 . . . lsb+1 lsb response n miso . . . sclk zeros zeros zeros zeros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . command write: response read:
SI4684-A10 24 rev. 1.0 figure 10. si4684 spi control interface bus protocol ? spi mode 1,1 ssb msb msb-1 . . . lsb+1 lsb command (write) mosi msb msb-1 . . . lsb+1 lsb msb arg 1 msb-1 . . . lsb+1 lsb arg n miso zeros sclk ssb msb msb-1 . . . lsb+1 lsb 00 mosi . . . . . . . . . msb msb-1 . . . lsb+1 lsb msb status (response 0) msb-1 . . . lsb+1 lsb response n miso . . . sclk zeros zeros zeros zeros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . command write: response read:
SI4684-A10 rev. 1.0 25 6.2. i 2 c control bus the si4684 control interface operates in i 2 c mode when the smode pin is tied to vio. the si4684?s i 2 c bus interface supports a 7-bit device addressing procedure and is capable of operating at clock rates up to 400 khz. individual data transfers to and from the device are eight bits. the i 2 c bus consists of two wires: a serial clock line (scl) and a serial data line (sda). scl and sda are mapped to the sclk and mosi pins, respectively. 6.2.1. i 2 c device address selection four device i 2 c addresses are available, allowing up to four si4684 receivers to share the same i 2 c bus. the 7-bit device address consists of a 5-bit fixed part (a6:a2), fo llowed by a programmable 2-bit part (a1:a0). the bit which follows the device address indicates whether a read or write i 2 c operation occurs. the voltage on the a0 and a1 lines are used to set the programmable 2-bit part of the device address. the a0 and a1 lines are mapped to the miso and ssb pins, respectively . a0 and a1 are tied to ei ther gnd or vio for address selection. the various i 2 c device addresses can be selected as summarized in table 13. table 13. i 2 c device address selection a6:a2 a1:a0 a1 voltage (pin connection) a0 voltage (pin connection) 11001 11 vio vio 11001 10 vio gnd 11001 01 gnd vio 11001 00 gnd gnd
SI4684-A10 26 rev. 1.0 6.2.2. i 2 c standard operation an i 2 c bus transaction begins with the start condition, whic h occurs when sda falls while scl is high. next, the user drives an 8-bit control byte serially on sda, which is captured by the external device on rising edges of scl. the control byte consists of a 7-bit device address followed by a read/write bit (read = 1, write = 0). the si4684 acknowledges the control word by driving sda low on the next falling edge of scl. read and write operations are performed in accordance with the i 2 c bus specification. for write operations, the external device sends an 8-bit data byte on sda, which is captured by the si4684 on rising edges of scl. the si4684 acknowledges each data byte by driving sda low for one cycle, after the next falling edge of scl. the external device may write any number of data bytes in a single 2-wire transaction. the first byte is a command, and the next bytes are arguments. for read operations, after the si4684 has acknowledged the control byte, it drives an 8-bit data byte on sda, changing the state of sda after the falling edge of scl. the external device acknowledg es each data byte by driving sda low for one cycle, after the next falling edge of scl. if a data byte is not acknowled ged, the transaction ends. the external device may read any number of data bytes in a single 2-wire transaction. these bytes contain the response data from the si4684. a 2-wire transaction e nds with the stop condition, which occurs when sda rises while scl is high. figure 11. i 2 c command/response protocol s device addr w a cmd a arg1 a arg2 a a p write operation s device addr r a status0 a status1 a status2 a n p read operation master slave a = acknowledge r = read w = write n = not acknowledge s = start condition a status3 a resp4 a arg3 a arg4 p = stop condition
SI4684-A10 rev. 1.0 27 6.3. programming to ease development time and offer maximum customizatio n, the si4684 provides a simple and powerful software command protocol in addition to the spi and i 2 c control interfaces to communicate with an external controller. the device is programmed using commands, arguments, proper ties, and responses. to perform an action, the user writes a command byte and associated arguments, caus ing the chip to execute the given command. commands control actions such as start-up and shut-down, and tune to a station. arguments are specific to a given command and are used to modify the command. properties are a special command + argument used to modify the default chip operation and are generally configured immediately after powerup. examples of properties are de-emphasis level, rssi seek threshold, and soft mute attenuati on threshold. after a command and arguments have been sent to the chip and processed, the user ma y read a response. the first 32 bits of the response contain the status field, which begins with the clear-to-send (cts) bit. cts = ?1? indicates that the remaining bytes of response contain valid information and that the chip is ready to receive a new command. 6.4. serial flash interface the si4684 serial flash interface supports the synchron ous transfer of data between the part and an external serial flash memory via a 4-wire spi bus consisting of the following: ?? serial clock (nvsclk) ?? slave select (nvssb), a llows the si4684 to se lect a slave device ?? master data input pin (nvmiso) ?? master data output pin (nvmosi) the si4684 serial flash interface sup ports spi mode 3 (cpha = 1, cpol = 1).
SI4684-A10 28 rev. 1.0 6.5. reset timi ng and power states the si4684 supports three power states: ?? reset ?? startup ?? operational 6.5.1. reset the si4684 is in its lowest-power stat e when the rstb pin is asserted (held low). this is the reset state. all analog and digital circuitry is disabled, and the va, vc ore and vmem power supplies are internally disconnected to reduce leakage. 6.5.2. startup deasserting (holding high) the rstb pin places the chip into the startup state, which is a temporary state that enables the si4684 to respond to the power_up command, and other commands to load software and boot the si4684. 6.5.3. operational after software has been loaded, the boot command caus es the si4684 to enter the operational state, which is the highest-powe r state. the si4684 can be retu rned to the reset state by as serting (holding low) the rstb pin. figure 12 shows required reset, startup, and shutdown timings for the si4684. rstb must be held low (asserted) during any power supply transitions and remain asserted for 10 s after all power supplies are stable as specified in figure 12. failure to assert rstb as indicated he re may cause the device to malfunction and may result in permanent device damage. figure 12. reset, startup, and shutdown timing table 14 shows typical startup power state, power_up command, and boot command timings. command reset pow er state load_init pow er_up host_load rstb va, vcore vmem, vi o =10 s t rstb_hi:pow er_up boot operati onal startup reset >0 s t reset: boot_cts t pow er_up t boot t psup: rstb_hi t rstb_lo: psdn
SI4684-A10 rev. 1.0 29 table 14. startup power state, power_up command, and boot command timings parameter symbol analog fm dab unit power supplies ramped up and stable to rstb rise t psup:rstb_hi 10 s rstb fall to start of power supplies ramp down t rstb_lo:psdn 0 s rstb rise to start of power_up command 1 t rstb_hi:power_up 55m s start of power_up command to end of power_up command 1 t power_up 33.2ms start of boot command to end of boot command 1 t boot 63 269 ms rstb rise to end of boot command clear-to-send (cts) 1,2,3,4,5,6 t reset:boot_cts 745 965 ms notes: 1. characteristics apply to firmware fm 2.0.10 and firmware dab 1.0.6. for later firmware versions see "si468x data sheet addendum". 2. firmware downloaded with spi bus @ 10 mhz clock rate. 3. spi bus transactions clocked as one continuous block of data. 4. cts polled between each command. 5. additional delay between cts polls @ 1 ms. 6. host_load commands sent with 4092-byte payloads.
SI4684-A10 30 rev. 1.0 7. pin descriptions 7.1. SI4684-A10-gm pin description figure 13. SI4684-A10-gm pinout table 15. pin descriptions for SI4684-A10-gm pin number pin name i/o description 1 nvssb o spi slave select for serial flash 2 nvsclk o spi clock for serial flash 3 intb o host irq 4 rstb i active low reset signal 5 smode i smode = 0 spi, smode = 1 i 2 c to control si4684 6 rfref pwr rf ground reference 7 rfref pwr rf ground reference 8 rfref pwr rf ground reference 9 rfref pwr rf ground reference 10 vhfi i vhf lna input 11 vhfsw o vhf front-end switch; 0 switch open; 1 switch closed 12 va pwr analog supply voltage 13 abyp pwr analog bypass 48 47 46 45 43 42 41 40 39 38 44 37 1 2 3 5 6 7 8 9 10 11 12 4 13 14 15 16 18 19 20 21 22 23 17 24 36 35 34 32 31 30 29 28 27 26 25 33 dbyp vmem vio dout miso mosi sclk ssb dfs dclk nc nc nvmosi nvmiso nc nc nc nc gndd gndd gndd gndd nc vcore abyp nc xtali xtalo dacref lout rout nc nc nc nc nc nvssb nvsclk intb rstb smode rfref rfref rfref rfref vhfi vhfsw va
SI4684-A10 rev. 1.0 31 14 nc nc no connect; leave floating 15 xtali i crystal amp input 16 xtalo o crystal amp output 17 dacref pwr dac reference supply voltage 18 lout o left channel audio dac output (powered from va) 19 rout o right channel audio dac output (powered from va) 20 nc nc no connect; leave floating 21 nc nc no connect; leave floating 22 nc nc no connect; leave floating 23 nc nc no connect; leave floating 24 nc nc no connect; leave floating 25 nc nc no connect; leave floating 26 nc nc no connect; leave floating 27 dclk i/o i 2 s clock for digital audio 28 dfs i/o i 2 s frame sync for digital audio 29 ssb i spi slave select or i 2 c address a1 30 sclk i spi or i 2 c clock input 31 mosi i/o spi data input or i 2 c data i/o 32 miso i/o spi data output or i 2 c address a0 33 dout o i 2 s audio output 34 vio pwr interface supply voltage 35 vmem pwr memory supply voltage 36 dbyp pwr digital bypass 37 vcore pwr digital core supply voltage 38 nc nc no connect; leave floating 39 gndd pwr digital ground 40 gndd pwr digital ground 41 gndd pwr digital ground 42 gndd pwr digital ground 43 nc nc no connect; leave floating 44 nc nc no connect; leave floating 45 nc nc no connect; leave floating 46 nc nc no connect; leave floating 47 nvmiso i spi master data input for serial flash 48 nvmosi o spi master data output for serial flash table 15. pin descriptions for SI4684-A10-gm (continued) pin number pin name i/o description
SI4684-A10 32 rev. 1.0 7.2. SI4684-A10- gd pin description figure 14. SI4684-A10-gd pinout table 16. pin descriptions for SI4684-A10-gd pin number pin name i/o description a1 nc nc no connect; leave floating a2 intb o host irq a3 gnda pwr analog ground a4 rfref pwr rf ground reference a5 rfref pwr rf ground reference a6 rfref pwr rf ground reference a7 vhfi i vhf lna input a8 va pwr analog supply voltage a9 gnda pwr analog ground b1 gndd pwr digital ground b2 nc nc no connect; leave floating b3 gnda pwr analog ground b4 gnda pwr analog ground a 9 8 7 6 5 4 3 2 1 gnda va vhfi rfref rfref rfref gnda intb nc gnda vhfsw rfref gnda gnda gnda nc gndd gnda xtali gnda gnda gnda nvsclk nc nc gndd xtalo gnda nvmosi nvssb nvmiso nc gndd gndd lout rout gnda rstb smode ssb mosi miso vcore gnda gnda nc nc nc dclk sclk gndd vmem nc nc nc nc nc dfs dout vio dbyp bcdefg dacref
SI4684-A10 rev. 1.0 33 b5 gnda pwr analog ground b6 rfref pwr rf ground reference b7 vhfsw o vhf front-end switch; 0 switch open; 1 switch closed b8 gnda pwr analog ground b9 nc nc no connect; leave floating c1 gndd pwr digital ground c2 nc nc no connect; leave floating c3 nc nc no connect; leave floating c4 nvsclk o spi clock for serial flash c5 gnda pwr analog ground c6 gnda pwr analog ground c7 gnda pwr analog ground c8 xtali i crystal amp input c9 gnda pwr analog ground d1 gndd pwr digital ground d2 gndd pwr digital ground d3 nc nc no connect; leave floating d4 nvmiso i spi master data input for serial flash d5 nvssb o spi slave select for serial flash d6 nvmosi o spi master data output for serial flash d7 gnda pwr analog ground d8 dacref pwr dac reference supply voltage d9 xtalo o crystal amp output e1 vcore pwr digital core supply voltage e2 miso i/o spi data output or i 2 c address a0 e3 mosi i/o spi data input or i 2 c data i/o e4 ssb i spi slave select or i 2 c address a1 e5 smode i smode = 0 spi, smode = 1 i 2 c to control si4684 e6 rstb i active low reset signal e7 gnda pwr analog ground e8 rout o right channel audio dac output (powered from va) e9 lout o left channel audio dac output (powered from va) table 16. pin descriptions for SI4684-A10-gd (continued) pin number pin name i/o description
SI4684-A10 34 rev. 1.0 f1 vmem pwr memory supply voltage f2 gndd pwr digital ground f3 sclk i spi or i 2 c clock input f4 dclk i/o i 2 s clock for digital audio f5 nc nc no connect; leave floating f6 nc nc no connect; leave floating f7 nc nc no connect; leave floating f8 gnda pwr analog ground f9 gnda pwr analog ground g1 dbyp pwr digital bypass g2 vio pwr interface supply voltage g3 dout o i 2 s audio output g4 dfs i/o i 2 s frame sync for digital audio g5 nc nc no connect; leave floating g6 nc nc no connect; leave floating g7 nc nc no connect; leave floating g8 nc nc no connect; leave floating g9 nc nc no connect; leave floating table 16. pin descriptions for SI4684-A10-gd (continued) pin number pin name i/o description
SI4684-A10 rev. 1.0 35 8. ordering guide part number * description package type operating temperature SI4684-A10-gm fm/dab/dab+ digital radio receiver with rds/ rbds qfn pb-free ?40 to 85 c SI4684-A10-gd fm/dab/dab+ digital radio receiver with rds/ rbds wlcsp pb-free ?40 to 85 c *note: add an ?r? at the end of the device part number to denote tape-and-reel option.
SI4684-A10 36 rev. 1.0 9. package outlines 9.1. SI4684-A10- gm package outline figure 15 illustrates the package details for the si4684. table 18 lists the valu es for the dimensions shown in the illustration. figure 15. 7 x 7 mm 48-pin qfn
SI4684-A10 rev. 1.0 37 table 17. package dimensions dimension millimeters min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d7 . 0 0 b s c d2 5.20 5.30 5.40 e0 . 5 0 b s c e7 . 0 0 b s c e2 5.20 5.30 5.40 l 0.30 0.40 0.50 aaa 0.15 bbb 0.10 ddd 0.05 eee 0.08 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994 3. this drawing conforms to the jedec solid state outline mo-220, variation vkkd-4. 4. recommended card reflow profile is per t he jedec/ipc j-std-0 20 specification for small body components.
SI4684-A10 38 rev. 1.0 9.2. SI4684-A10-gd package outline figure 16 illustrates the package details for the si4684. table 18 lists the valu es for the dimensions shown in the illustration. figure 16. 3.2 x 3.7 mm 62-ball wlcsp
SI4684-A10 rev. 1.0 39 table 18. package dimensions dimension millimeters min nom max a 0.55 0.59 0.63 a1 0.18 0.20 0.22 b 0.22 0.27 0.32 d 3.20 bsc e 3.77 bsc d 0.40 bsc e 0.40 bsc d1 2.40 bsc e1 3.20 bsc aaa 0.10 bbb 0.10 ccc 0.03 ddd 0.15 eee 0.05 notes: 1. all dimensions shown are in m illimeters (mm) unle ss otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. primary datum ?c? and seating pl ane are defined by the spherical crowns of the solder balls. 4. dimension ?b? is measured at the maximum solder bump diameter, parallel to primary datum ?c?. 5. recommended card reflow profile is per the jedec/ipc j-std-020 specif ication for small body components.
SI4684-A10 40 rev. 1.0 10. pcb land patterns 10.1. SI4684-A10-gm pcb land pattern figure 17 illustrates the pcb land pattern details for the si4684. table 19 lists the values for the dimensions shown in the illustration. figure 17. pcb land pattern ?
SI4684-A10 rev. 1.0 41 table 19. pcb land pattern dimensions dimension millimeters min max c1 6.80 6.90 c2 6.80 6.90 e0 . 5 0 b s c x1 0.20 0.30 x2 5.20 5.40 y1 0.75 0.85 y2 5.20 5.40 notes: general: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is bas ed on the ipc-7351 guidelines. solder mask design: 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. solder mask design: 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. a 4x4 array of 1.1 mm square openings on 1.3 m m pitch should be used for the center ground pad. solder mask design: 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
SI4684-A10 42 rev. 1.0 10.2. SI4684-A10-gd pcb land pattern figure 18 illustrates the pcb land pattern details for the si4684. table 20 lists the values for the dimensions shown in the illustration. figure 18. pcb land pattern ?
SI4684-A10 rev. 1.0 43 table 20. pcb land pattern dimensions dimension millimeters min nom max x 0.23 0.24 0.25 c1 2.40 c2 3.20 e1 0.40 e2 0.40 notes: general: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensions and tolerancing is per th e ansi y14.5m-199 4 specification. 3. this land pattern design is based on the ipc-7351 guidelines. solder mask design: 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design: 5. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1. card assembly: 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std-020 specif ication for small body components.
SI4684-A10 44 rev. 1.0 11. top markings 11.1. SI4684-A10-gm top marking 11.2. SI4684-A10-gm top mark explanation mark method: yag laser line 1 marking: part number (right-justified) 4684 = si4684 a = part revision a 10 = firmware revision 1.0 line 2 marking: yy = year ww = work week tttttt = mfg code assigned by the assembly hous e. corresponds to the year and work week of the assembly date. manufacturing code from the assembly purchase order form. line 3 marking: circle = 1.3 mm diameter (center justified) ?e3? pb-free symbol country of origin iso code abbreviation cc = country code (e.g., ?tw? for taiwan) pin 1 mark: circle = 0.70 mm diameter (bottom left-justified) ?
SI4684-A10 rev. 1.0 45 11.3. SI4684-A10-gd top marking 11.4. SI4684-A10-gd to p marking explanation mark method: yag laser line 1 marking: part number (right-justified) 4684 = si4684 10 = firmware revision 1.0 line 2 marking: a ttttt = mfg code a = part revision a manufacturing code from the assembly purchase order form. line 3 marking: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the assembly date. pin 1 mark: right triangle = 0.50 mm equal sides (bottom left-justified) ?
SI4684-A10 46 rev. 1.0 d ocument c hange l ist revision 0.6 to revision 0.7 ?? updated the typical application schematic to reflect the newly recommended front-end network ?? updated the audio interface section to remove all unsupported audio data formats ?? updated the part number for the qfn version ?? updated the top marking drawings revision 0.7 to revision 0.8 ?? added the junction temperature test condition and max limit spec for the wlcsp package to table 10 on page 15. ?? updated the max current limits for the analog fm mode on page 5. ?? updated the applications list on the cover page. ?? updated the functional block diagram on page 2 and page 17. revision 0.8 to revision 1.0 ?? added voltage and current specs for the digital pins. ?? updated the control interfac e description on p.23 for improved accuracy. ?? changed the frequency cited in note 2 of table 8 on page 12 from 98.0 mhz to 195.936 mhz. ?? fixed the direction of t he ssb and miso signals in the functional block diagram in p.2 and p.18. ?? fixed the i 2 s digital audio and serial flash interface timing diagrams on p.9 and p.10, respectively. ?? augmented the description, figure and table in section "6.5. reset timing and power states" on page 28 with additional reset timing information.
SI4684-A10 rev. 1.0 47 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our customers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive patent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believ ed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon labor atories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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